1. Field of the Invention
The present invention relates generally to interface structures connected to a pad of a semiconductor device, and, in particular, to an input/output cell tolerant to high voltages applied to the pad.
2. Description of the Related Art
With the advancement of microelectronic devices, due in part to shrinking geometries, and the need for reduced power dissipation, a 3.3 volt operating voltage standard has emerged as an alternate standard to the ubiquitous 5 volt standard that has existed for many years. In a mixed operating voltage environment where both a 5 volt rail and a 3 volt rail exist, a 5 volt signal may be applied to a pin designed for 3 volts. This application of a relatively high voltage to a low voltage pin may occur by design, such as where 3.3 volt devices, as well as 5 volt devices share a common bus, or, alternatively, unintentionally, such as may occur during "live insertion," or, by other accident wherein a 5 volt signal is cross-connected to such a low voltage pin. The above-referenced "high" voltage may be defined as any voltage level that is greater than the V.sub.cc /operating voltage of the device.
Thus, designers of such microelectronic devices, and, in particular, the designers of interface structures, such as input/output (I/O) cells employed in such devices, have remained cognizant of such high voltage applications to low voltage pins.
One problem arising in view of the foregoing relates to the "pullup" circuit portion of the I/O cell. In particular, the specific problem relates to the use of a p-channel FET as the pullup device on a 3.3 volt operating voltage device when a relatively higher voltage, such as a 5.0 volt signal, is applied to the pin of such a device. Consider that the pullup p-channel transistor is formed in an n-well, which may be tied to V.sub.cc (e.g., 3.3 volts for a 3.3 volt part). When a 5 volt signal appears on the I/O pad, it is coupled to the drain p.sub.+ region of the pullup p-channel transistor. Large currents flow when this situation occurs for two reasons. First, a p-n junction, formed by the source/drain p.sup.+ and the n-well region, will be forward biased and will conduct a significant amount of current. Second, the p-channel pullup device itself may be turned "ON," since the gate voltage (which will have, at most, V.sub.cc applied thereto) will be lower than the drain terminal (connected to the I/O pad) by more than the device threshold level wherein the transistor conducts, thus shorting the high voltage on the output pad to the internal power supply rail (3.3 volt rail).
For 5 volt devices, conventional I/O cell designs have used an n-channel field effect transistor (FET) as the "pullup" transistor so the above problem does not occur. This design choice is acceptable for 5 volt devices since the pad, which is connected to the I/O cell, need not be pulled all the way up to 5 volts in most applications; that is, the reduction in output potential relative to V.sub.cc due to the requirement that V.sub.gs &gt;V.sub.tn of the n-channel device used as a pullup device to keep it "on" still provides a high enough output voltage to define a logic high output state (i.e., V.sub.OH). However, with respect to 3.3 volt devices, the limitations of the n-channel device are unacceptable. In particular, the lowered output relative to the 3.3 volt V.sub.cc does not permit the I/O cell to drive the output pad to a high enough level to meet most V.sub.OH requirements.
Thus, it would be desirable to use a p-channel device as the "pullup" device for 3.3 volt parts but the above-described problems relating to high voltages (e.g., 5 volts) applied to low voltage (3.3 volt) I/O cells have circumscribed its use in the 3.3 volt environment for some applications.
One solution taken by the art in solving the above problems is to use a pumped n-channel pullup device for 3.3 volt devices wherein a high voltage gate drive signal, derived from a charge pump, is used to provide a full-rail swing to 3.3 volts on the output pad. A problem with this approach, however, is that a substantial dynamic current is required from the charge pump circuit to raise the n-channel transistor gate sufficiently above V.sub.cc so that the input/output pad can be pulled all the way to V.sub.cc. Some current is also required even when the pullup transistor is not switching to combat leakage so that a static current (I.sub.cc) drawn by such a microelectronic device may be relatively large--sometimes unacceptably large for a chip that is supposed to draw very few microamps when it is not switching.
Accordingly, there is a need to provide an I/O cell structure that minimizes or eliminates one or more of the problems as described above.